Building a Full-System RISC-V Simulation Platform from Scratch

Inspired by open-source processor projects such as XiangShan, BOOM, and CVA6, we built a RISC-V full-system simulation platform from scratch. The goal of this platform is to support processor design, software deployment, RTL verification, and performance exploration. It includes a RISC-V instruction set simulator capable of booting Linux and FreeRTOS, and has successfully integrated two in-house RTL RISC-V cores: a 6-stage in-order processor capable of booting Linux, and an 11-stage out-of-order processor capable of booting FreeRTOS.

At the system level, we use Verilator to compile the RTL core into a C++ model, and use SystemC to build the bus and peripheral devices. This allows the RTL design to perform full-system simulation at the C++ level and successfully boot within one hour. To accelerate processor development, we also built a co-simulation mechanism. Whenever the core commits an instruction, the architectural state is compared against the instruction set simulator in real time. When an error occurs in the core, the simulation can stop immediately and provide debugging information.

In this talk, we will share the architecture of the platform, our experience booting Linux and FreeRTOS, the RTL co-simulation debugging flow, and how we implemented a high-performance non-blocking cache model in C++ with configurable cache size, associativity, hit latency, replacement policy, and prefetcher. We will also demonstrate how Konata can be used to observe the pipelined behavior of the core and cache, and how DRAMSys is integrated to perform performance evaluation under conditions closer to a real system.