c4c: the smallest full feature C++ compiler for x86, arm and RISC-V based xPU

Are modern compilers really designed for xPU?

New-generation AI accelerators like Google TPU, Meta MTIA, and Tesla Dojo increasingly adopt a hybrid architecture—RISC-V combined with Tensor Cores—to balance flexibility and performance. In theory, this allows developers to reuse mature toolchains like LLVM/MLIR, avoiding the need to build custom compilers from scratch.

In practice, the opposite happens.

The performance-critical path on xPU depends heavily on hardware-specific optimizations: memory layout, DMA orchestration, software pipelines, and register control. These are difficult for general-purpose compilers to infer. Developers inevitably fall back to handwritten inline assembly—fighting the toolchain instead of leveraging it.

This talk explores that gap and rethinks the role of the compiler. If optimization is inherently hardware-specific, should the compiler be redesigned around that reality?

After spending two years wrestling with LLVM, I made a decision: if modern LLMs can already write C compilers, why not build one that actually understands xPU?

This is not just about building a new toolchain—it’s about redefining what a compiler should be.